Random access memory ("RAM") is commonly implemented within computer systems of the prior art. Computer systems may employ a multi-level hierarchy of memory, with relatively fast, expensive but limited-capacity memory at the highest level of the hierarchy and proceeding to relatively slower, lower cost but higher-capacity memory at the lowest level of the hierarchy. The hierarchy may include a small fast memory called a cache, either physically integrated within a processor or mounted physically close to the processor for speed. The computer system may employ separate instruction caches ("I-caches") and data caches ("D-caches"). In addition, the computer system may use multiple levels of caches. The use of a cache is generally transparent to a computer program at the instruction level and can thus be added to a computer architecture without changing the instruction set or requiring modification to existing programs. Generally, RAM may be implemented within any such level of a multi-level hierarchy of memory utilized for a computer system.
Various RAM chips have been developed in the prior art to allow data to be moved in and out of memory quickly, to avoid errors, and to make collections of RAM chips smaller. The most common types of RAM include dynamic random access memory (DRAM), Extended Data Out random access memory (EDO RAM), video random access memory (VRAM), static random access memory (SRAM), synchronous DRAM (SDRAM), single in-line memory modules (SIMM), dual in-line memory modules (DIMM), and error-correcting code (ECC) chips. It is common in manufacturing (or "fabricating") a RAM chip that a defect may occur within a portion of the chip. That is, a portion of the RAM may not allow for the proper storage and/or retrieval of data. Accordingly, techniques have been developed in the prior art for detecting and correcting such defects. Generally, redundancy is desired in a chip or system with a large number of memory or circuit blocks where a defective block could be mapped to a non-defective block to improve the manufacturing yield and/or to keep a system operating properly. Typically, RAM memory is implemented in such a redundant system, and therefore the following description of the prior art focuses primarily on RAM memory implementations. However, it should be recognized that various other types of memory may be implemented with redundancy as well.
A common technique that is utilized in the prior art to correct defects detected in RAM chips is to provide redundant sub-blocks of memory within a RAM chip, which can be used to effectively replace a defective sub-block of memory within the chip. Turning to FIG. 1, an exemplary overview of implementing redundant sub-blocks within a RAM structure is shown. As shown, a very large RAM block (or RAM structure) 300 may be implemented within a chip. If a defect is present in the RAM block 300, it is desirable to be capable of repairing it to improve the yield of the die, and once it is determined that RAM 300 either has no defects or all of its defects have been repaired, to then ship the chip or system that includes RAM 300 to a customer. Repairing a defective RAM block 300 may be accomplished by providing a group of redundant sub-blocks, such as sub-blocks 310, 312, and 314, which may be used to replace a defective sub-block within RAM block 300. Accordingly, the term "repair" as used herein should not be read narrowly to mean physically repairing a defective sub-block, but should instead be read more broadly to encompass avoiding a defective sub-block. Ideally, it would be desirable to be capable of repairing any defective location in the RAM block 300 with any one of the redundant sub-blocks (e.g., any one of sub-blocks 310, 312, 314, etc.). However, a problem arises when shipping data (i.e., "memory data") from a defective sub-block within RAM block 300 to a redundant sub-block that is physically located at a relatively far distance away. That is, when a redundant sub-block is located relatively far away from a defective sub-block, the latency involved in transporting data such a long distance has a negative impact on the system's performance.
For example, suppose a defect occurs within sub-block 350 of RAM 300, which is physically located a relatively far distance away from the redundant sub-blocks (310, 312, 314, etc.). To repair sub-block 350, write data would have to be shipped from the port of sub-block 350 all the way over to a redundant sub-block, such as redundant sub-block 310, and read data would have to be shipped out from the redundant sub-block 310 to the port of sub-block 350 so it can be driven to its desired destination on the chip. The additional latency (i.e., wiring delay) resulting from shipping data such a long distance can have a large, negative impact on the performance of the system. That is, the additional latency resulting from shipping data a relatively long distance from a defective location to a redundant sub-block increases the amount of time required to access data within the redundant sub-block, thereby slowing the operating speed of the system.
Turning to FIG. 2, a design of the prior art that utilizes redundant sub-blocks to repair a RAM block 300 is illustrated. In the solution of FIG. 2, a large RAM block 300 is partitioned into smaller segments (or "banks"), such as segments 302, 304, 306 and 308. For each one of the segments 302, 304, 306, and 308, a redundant sub-block is assigned thereto. More specifically, redundant sub-block 310 is associated with segment 302, redundant sub-block 312 is associated with segment 304, redundant sub-block 314 is associated with segment 306, and redundant sub-block 316 is associated with segment 308. Accordingly, any defect in segment 302 can effectively be repaired with its redundant sub-block 310. Similarly, any defects within any of the other segments may be repaired using their respective associated redundant sub-blocks.
To further illustrate the operation of the prior art RAM design shown in FIG. 2, suppose that sub-block (or "sub-array") 321 within segment 302 is defective. Data is shifted from the nearest sub-block to the right of sub-block 321 to repair sub-block 321. That is, sub-block 320 is routed out to the input/output port (I/O port) of sub-block 321 through a MUX (not shown). Each of the remaining blocks to the right of sub-block 320 (i.e., sub-blocks 319 and 318 of FIG. 2) is shifted in a similar manner, and finally redundant sub-block 310 is shifted to provide the data for sub-block 318. Shifting of the nearest neighbor in this manner results in a relatively short routing length because data is only routed to a sub-block's nearest neighbor. Therefore, this prior art RAM design may be implemented to provide a high yield of a die by effectively allowing a defective RAM to be repaired.
It should be recognized that the exact manner in which the RAM block 300 is partitioned may vary. Typically, the number of segments in which a RAM block is partitioned is dependent on the number of functional units implemented for the RAM (e.g., the number of data cache units, tag cache units, etc.). More specifically, it is typically desirable to have the RAM segmented in a manner that allows for each functional unit to be repaired separately. For instance, the large RAM block 300 may be partitioned into six D-cache data segments, two I-cache data segments, two D-cache tag segments, and two I-cache tag segments. It should be recognized that any number of segments may be implemented in this manner. Typically, for a larger size RAM block 300, a greater number of segments are desirable in order to allow a high yield of the die. It should also be understood that each sub-block of a segment (e.g., sub-block 321, 320, 319, 318, 310, etc.) may actually comprise a group or "array" of memory cells. Thus, each sub-block may comprise X number of rows of memory cells by Y number of columns of memory cells. Accordingly, as used herein, the replaceable unit (or "repairable sub-block") may comprise an array of memory cells.
Turning to FIG. 3, a further example of the prior art implementation discussed with FIG. 2 is provided. FIG. 3 shows segment 302 of FIG. 2 in greater detail, but in the example shown in FIG. 3 sub-block 319 is defective, rather than sub-block 321. Thus, FIG. 3, shows repairable sub-blocks 330, 320, 319, and 318, as well as redundant sub-block 310 implemented for segment 302. A set of redundancy MUXes (e.g., MUXes 220, 222, 224, 226, 228, 230, 232, 234, and 236) are shown, which are utilized to reroute the actual data for a memory sub-block, which may be referred to herein as "memory data," if a defective subblock is detected within segment 302. In the example shown in FIG. 3, sub-block 330 is a good (non-defective) sub-block. Accordingly, the redundancy MUX 222 is programmed such that the memory data is flowing from the internal signal 18a of sub-block 330 through MUX 222 to "data out (DOUT)" signal 18b, which is the normal path for sub-block 330. Also, "data in (DIN)" signal 18c (which may also be considered "memory data") is received by MUX 220, which routes the DIN signal 18c to sub-block 330, thus routing the DIN signal 18c along the normal path for sub-block 330.
Similarly, sub-block 320 is a good (non-defective) sub-block. Accordingly, the redundancy MUX 226 is programmed such that the data is flowing from the internal signal 16a of sub-block 320 through MUX 226 to DOUT signal 16b, which is the normal path for sub-block 320. Also, DIN signal 16c is received by MUX 224, which routes the DIN signal 16c to sub-block 320, thus routing the DIN signal 16c along the normal path for sub-block 320. However, sub-block 319 is defective. Therefore, MUX 230 is programmed to output the DOUT signal from the nearest neighbor of sub-block 319, i.e., sub-block 318. That is, MUX 230 is programmed to route the internal DOUT signal 12a of sub-block 318 to DOUT signal 14b, rather than routing the internal DOUT signal 14a of defective sub-block 319 to DOUT signal 14b. Also, MUX 228 is turned off, and MUX 232 is programmed to route received DIN signals 14c to sub-block 318 instead of defective sub-block 319.
Because sub-block 318 has been effectively shifted to replace defective sub-block 319, redundant sub-block 310 is shifted to take the place of sub-block 318. To accomplish such a shift, MUX 234 is programmed to route the internal DOUT signal 10a of redundant sub-block 310 to DOUT signal 12b, rather than routing the internal data out signal 12a of sub-block 318 to DOUT signal 12b. Also, MUX 236 is programmed to route received DIN signals 12c to redundant sub-block 310 instead of sub-block 318. As a result, the data produced by the defective sub-block 319 is completely ignored. Additionally, data is only shifted by one sub-block in order to repair the defect, which produces very little latency in shipping the data. Moreover, 2:1 MUXes are implemented to allow for such a shift, which are fairly simple and have very little impact on performance (i.e., delays the signals very little).
Fuses are typically implemented in the RAM design to control the redundancy MUXes. Traditionally, laser-blown fuses have been utilized. Several problems exist with utilizing laser-blown fuses in the prior art implementation of FIG. 3. First, such laser-blown fuses are very small in size, but a large number of such fuses have traditionally been required. Additionally, laser-blown fuses must be blown at the wafer level of manufacturing a chip (i.e., before packaging). That is, laser-blown fuses can only be blown at the wafer level because once the circuitry is in its packaging, it is very difficult to get a laser to shine onto the die appropriately. Therefore, laser-blown fuses allow a manufacturer only one shot to detect and fix a defective RAM, i.e., during the wafer level. This is further problematic because the wafer level typically does not provide the most desirable electrical environment for detecting defects in the RAM. Therefore, it is possible that defects present in the RAM may not show up at the wafer stage, but show up later in the packaging stage. Electrically-blown fuses have been implemented within such a prior art RAM design. Electrically-blown fuses allow a manufacturer the flexibility of blowing the fuses at any point in time. Thus, a manufacturer may blow an electrically-blown fuse at a later stage than is possible with laser-blown fuses (e.g., after the packaging stage). However, electrically-blown fuses are much larger in size than laser-blown fuses because of the circuitry required to provide the larger currents needed to reliably blow each fuse.
One problem with the prior art implementation illustrated in FIG. 3 is that it requires one fuse to be implemented for each of the repairable sub-blocks. Accordingly, a large RAM typically requires a large number of fuses. However, only a small number of such fuses will typically be required to be blown. For example, in the case of defective sub-block 319 of FIG. 3, only fuse 20 is required to be blown, but the remaining fuses are required to be present in the RAM design in case a defect had been detected for one of the other sub-blocks. Requiring such a large number of fuses is particularly problematic when implementing the larger, electrically-blown fuses because of the relatively large amount of surface area required on the chip for such fuses.
Continuing with the discussion of the prior art design of FIG. 3, a scan path 22 is shown in the design. Scan path 22 typically comprises serial shift registers that allow data to be scanned in to program the redundancy MUXes from a controller that may be provided somewhere on the chip. Such scan path 22 may allow a manufacturer the ability to verify the appropriate control signals for the redundancy MUXes before actually blowing a fuse to set the control for the redundancy MUXes. That is, scan path 22 allows a manufacturer to scan in a set of control signals to ensure that such control signals do indeed repair the defective RAM correctly before blowing any fuses to actually set such control signals for the RAM. For example, in the case illustrated in FIG. 3 in which a defect exists in sub-block 319, the appropriate number of zeros followed by the appropriate number of ones may be scanned into the scan chain 22 to ensure that blowing fuse 20 would, in fact, repair such defect prior to actually blowing fuse 20.
In operation of such prior art RAM implementation, the fuse chain is pulled down to ground (GND) during reset. If none of the fuses are blown, then the entire fuse chain gets pulled down, and all zeros are programmed into the scan path latches. Accordingly, none of the redundancy MUXes are programmed to perform a shift. In the case where fuse 20 is blown, all of the traces of the fuse chain before the blown fuse 20 are pulled down, and all of the traces after the fuse chain 20 are pulled high. Therefore, the appropriate number of zeros and ones are loaded into the scan path latches causing the redundancy MUXes to perform the appropriate shift to repair the defective sub-block 319. Of course, if none of the sub-blocks are defective, then none of the fuses in fuse chain 20 are blown.
A further advancement made in the prior art is to implement a state machine to shift the data through the scan path. Turning to FIG. 4, this further advancement of the prior art is shown. In this prior art RAM design, a binary-coded number of fuses are utilized to program the position where the defect is located into the scan chain 22 using a state machine 210. As with the example shown in FIG. 3, in the example of FIG. 4 sub-block 319 is defective and the remaining sub-blocks are good (non-defective). Because sub-block 319 is defective, state machine 210 scans in a 1 (a high voltage value) to the corresponding scan latch for sub-block 319, as well as all of the scan latches for the following sub-blocks (i.e., sub-blocks 318 and 310). Accordingly, by blowing the appropriate fuses for state machine 210, the appropriate values can be provided to the scan chain latches 22 to control the redundancy MUXes in order to correct a defect within the RAM segment 302. Again, if none of the sub-blocks were defective, then none of the fuses are blown.
Because the fuses implemented in this design are arranged to binary code the desired values for the scan latches to control the redundancy MUXes, a fewer number of fuses are required than in the prior art design illustrated in FIG. 3. For example, if segment 302 contained 256 repairable sub-blocks, only nine fuses would be required to control the redundancy MUXes for segment 302. Accordingly, the number of fuses required to control the redundancy MUXes for a segment 302 can be calculated as log to the base 2 of 1 plus the number of sub-blocks within the segment. That is, in this prior art design, only "J" fuses are required to provide redundancy for 2.sup.J -1 sub-blocks of a segment of RAM, i.e., nine fuses for each segment having 256 sub-blocks (2.sup.9 -1 sub-blocks). A further advantage of this prior art design is that any sub-block within segment 302 may be repaired without requiring the state machine 210 and its fuses to be positioned physically close to the redundancy MUXes of segment 302. Typically, the scan paths 22 are shifted at relatively low frequencies at power up. A start pulse is typically triggered at reset, which is fed to state machine 210. A clock signal is also fed to the state machine 210, such that upon the start pulse being input to state machine 210 it reads its fuses and utilizes the clock signal to scan out the appropriate number of 1's and 0's to the scan chain 22. While state machine 210 produces some additional overhead within the circuitry, it is typically a relatively small component and can be placed anywhere on the chip. Accordingly, the state machine 210 is not required to be placed within the memory array itself, thereby not increasing the overhead for the memory array itself, which aids in maintaining the performance of the memory array high.
However, there are still some problems with the prior art implementation of FIG. 4. One problem is that only one defect can be repaired within a sub-block. As a result, a large RAM block may be partitioned into many smaller segments, such as segment 302. As a large number of segments are implemented for a RAM block, the number of fuses required for the RAM block implementation increases. For example, if the RAM is implemented with 16 segments having 256 sub-blocks each, then nine fuses are required for each segment, for a total of 144 fuses that must be implemented in the RAM design to control the redundancy MUXes. For instance, FIG. 5 illustrates an overview of such prior art design implemented for a RAM block 300 that is partitioned into sixteen segments (i.e., segments 500, 501, 502, . . . 515) having 256 sub-blocks each. As shown, sixteen state machines (i.e., state machines 210, 211, 212, . . . 215) are implemented having nine fuses each, for a total of 144 fuses. As shown in FIG. 5, state machine 210 controls the redundancy MUXes 400 for segment 500. State machine 211 controls the redundancy MUXes 401 for segment 501. State machine 212 controls the redundancy MUXes 402 for segment 502, and so on, through state machine 215, which controls redundancy MUXes 415 for segment 515. As also illustrated in FIG. 5, it should be understood that even though the prior art designs have been described thus far as providing redundant sub-block columns for a RAM segment, such prior art designs may instead be implemented to provide redundant sub-block rows for row redundancy utilizing redundancy MUXes 440, 441, 442, . . . 455.
Even though sixteen segments are implemented within the RAM design of FIG. 5, the probability of a defect occurring in all sixteen segments is very small. For example, on average, only 2, 3, 4, or 5 segments may have a defect. That is, when manufacturing a quantity of RAM chips, the average (or typical) number of defective segments within a chip may be very small. However, the probability of there being a defect in any one of the sixteen segments is equal. That is, the chances of a defect occurring in any given segment are equal. Accordingly, the RAM block must be designed in a manner such that any of the segments may be repaired, individually. Accordingly, an unnecessarily high number of fuses are required to be implemented in this prior art design because this design still requires that sufficient fuses be implemented to allow for all possible defects that may occur, rather than implementing only a sufficient number of fuses to correct the number of defects that are likely to occur within a RAM block. That is, a high number of fuses are required to be implemented within this prior art design, to give the possibility of repairing every segment, while many of the fuses are wasted because on average only a few of them are actually utilized to correct defects.